During the past decade, peripheral component interconnect (PCI) has provided a very successful general purpose input/output (I/O) interconnect standard. PCI is a general purpose I/O interconnect standard that utilizes PCI signaling technology, including a multi-drop, parallel bus implementation. Unfortunately, traditional multi-drop parallel bus technology is approaching its practical performance limits. In fact, the demands of emerging and future computing models will exceed the bandwidth and scalability limits that are inherent in multiple drop, parallel bus implementations.
Accordingly, it is clear that meeting future system performance needs requires I/O bandwidth that can scale with processing and application demands. Alongside these increasing performance demands, the enterprise server and communication markets require improved reliability, security and quality of service guarantees. Fortunately, technology advances and high speed point-to-point interconnects are enabling system designers to break away from the bandwidth limitations of multiple drop, parallel buses. To this end, system designers have discovered a high-performance, third generation I/O (3GIO) interconnect that will serve as a general purpose I/O interconnect for a wide variety of future computing and communications platforms.
3GIO comprehends the many I/O requirements presented across the spectrum of computing and communications platforms and rolls them into a common scalable and extensible I/O industry specification. One implementation of 3GIO is the PCI Express specification. The PCI Express basic physical layer consists of a differential transmit pair and a differential receiver pair. As such, dual simplex data on these point-to-point connection referred to herein as a “point-to-point link,” is self-clocked and its bandwidth increases linearly with interconnect (link) width and frequency. In addition, PCI Express also provides a message space within its bus protocol that is used to implement legacy side band signals. As a result, a further reduction of signal pins produces a very low pin count connection for components and adapters.
Unfortunately, the use of a differential transmit pair and differential receive pair is a drastic deviation from traditional PCI. As a result, management of the serial (point-to-point) data links between transmit and receiver pairs utilizing traditional closed loop signaling may exceed the amount of latency tolerated by PCI Express. Moreover, power management envisioned using PCI Express cannot be supported utilizing traditional PCI techniques.
Furthermore, as point-to-point link speeds increase, it becomes more difficult to guarantee operation of the link by simply writing a link specification. Link-based systems, such as those based on PCI-E and, for example, cache coherent interconnect (CCI), have a mechanism where the transmitter transmits a “compliance pattern.” As described herein, a compliance pattern refers to a sequence of bits that characterize the transmitter to generate the worst case eye diagram. PCI-E, for example, provides techniques for determining compliance for, for example, generation one speeds of, for example, 2.5 Gigabits per second. Hence, merely providing a link specification does not ensure correct operation of point-to-point links as future generations operate at higher generation link speeds.